Serial interfaces receive serial bit streams. The serial bit streams are commonly loaded into address buffers and data latches so that they can be written in parallel into memory as individual bytes. The memory typically stores the individual bytes in a two dimensional memory array, which requires decoding in each of the two dimensions for both write and read operations.
It would be desirable to develop a new architecture to process serial bit streams without the overhead associated with address buffers, data latches and two dimensional decoders.